Generally, a field effect transistor (hereinafter, referred to as a transistor) of a semiconductor device may include source/drain regions that are spaced from each other at a semiconductor substrate (hereinafter, referred to as a substrate) and a gate electrode on a channel region between the source/drain regions.
As semiconductor devices become more highly integrated, sizes of transistors may be gradually reduced and these size reductions may result in problems. For example, a reduction in channel length may degrade a punch through characteristic between source/drain regions, and a controllability of a gate electrode with respect to a channel region may be degraded thereby increasing leakage currents. Fin field effect transistors (Fin FETs) have been introduced to address these issues.
A Fin FET includes a gate electrode crossing over a silicon fin protruding from a substrate. The silicon fin under the gate electrode corresponds to a channel region. The gate electrode passes over both sidewalls of the silicon fin. Because both sidewalls of the silicon fin can be used as a channel region controlled by the gate electrode, controllability of the gate electrode may be improved. A Fin FET may include source/drain regions of the silicon fin at both sides of the channel region. A characteristic such as punch through between the source/drain regions may thus be improved.
According to a conventional method of forming a Fin FET, a gate electrode may be formed after forming a silicon fin. That is, a gate conductive layer may be formed over the silicon fin, and patterned to form the gate electrode. The gate conductive layer may be patterned using an anisotropic etch process. During the patterning process, source/drain regions may be damaged due to over etch. More particularly, a gate insulation layer exposed at edges of the gate electrode and disposed on the silicon fin may be undesirably etched because the gate conductive layer disposed on both sidewalls of the protruding silicon fin may have a relatively high vertical height. If the thickness of a gate insulation layer at edges of the gate electrode is significantly reduced due to an over etch, a gate-induced drain leakage (GIDL) may increase thereby degrading characteristics of the Fin FET.
Additionally, a horizontal area between the source/drain regions may be relatively thin because the source/drain regions are formed in the silicon fin. A contact resistance between an upper conductor and the source/drain regions may also increase.